[ovs-dev] [PATCH] dpif-netdev-perf: aarch64 support for accurate timing update of TSC cycle counter

[Malvika Gupta]

The accurate timing implementation in this patch gets the wall clock counter via
cntvct_el0 register access. This call is portable to all aarch64 architectures
and has been verified on an 64-bit arm server.

Suggested-by: Yanqin Wei <yanqin.wei at arm.com>
Signed-off-by: Malvika Gupta <malvika.gupta at arm.com>
---
 lib/dpif-netdev-perf.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/lib/dpif-netdev-perf.h b/lib/dpif-netdev-perf.h
index ce369375b..4ea7cc355 100644
--- a/lib/dpif-netdev-perf.h
+++ b/lib/dpif-netdev-perf.h
@@ -220,6 +220,11 @@ cycles_counter_update(struct pmd_perf_stats *s)
     asm volatile("rdtsc" : "=a" (l), "=d" (h));
 
     return s->last_tsc = ((uint64_t) h << 32) | l;
+#elif !defined(_MSC_VER) && defined(__aarch64__)
+    uint64_t tsc;
+    asm volatile("mrs %0, cntvct_el0" : "=r" (tsc));
+
+    return s->last_tsc = tsc;
 #elif defined(__linux__)
     return rdtsc_syscall(s);
 #else
-- 
2.17.1